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MCP2021/2
LIN Transceiver with Voltage Regulator
Features
* The MCP2021 and MCP2022 are compliant with LIN Bus Specifications 1.3, 2.0, and 2.1 and are compliant to SAE J2602 * Support Baud Rates up to 20 Kbaud with LIN-compatible output driver * 43V load dump protected * Very low EMI meets stringent OEM requirements * Wide supply voltage, 6.0V - 18.0V continuous: - Maximum input voltage of 30V * Extended Temperature Range: -40 to +125C * Interface to PIC EUSART and standard USARTs * Local Interconnect Network (LIN) bus pin: - Internal pull-up resistor and diode - Protected against ground shorts - Protected against loss of ground - High current drive * Automatic thermal shutdown * On-Board Voltage Regulator: - Output voltage of 5.0V with tolerances of 3% overtemperature range - Available with alternate output voltage of 3.3V with tolerances of 3% overtemperature range - Maximum continuous input voltage of 30V - Internal thermal overload protection - Internal short circuit current limit - External components limited to filter capacitor only and load capacitor * Two low-power modes: - Receiver on, Transmitter off, voltage regulator on ( 85 A) - Receiver monitoring bus, Transmitter off, voltage regulator off ( 16 A)
Description
The MCP2021/2 provides a bidirectional, half-duplex communication physical interface to automotive, and industrial LIN systems to meet the LIN bus specification Revision 2.0. The device incorporates a voltage regulator with 5V @ 50 mA or 3.3V @ 50 mA regulated power supply output. The regulator is short circuit protected, and is protected by an internal thermal shutdown circuit. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections, +43V load dump transients, and double-battery jumps. The device has been designed to meet the stringent quiescent current requirements of the automotive industry. MCP2021/2 family members: * 8-pin PDIP, DFN and SOIC packages: - MCP2021-330, LIN-compatible driver, 8-pin, 3.3V regulator - MCP2021-500, LIN-compatible driver, 8-pin, 5.0V regulator * 14-lead PDIP, TSSOP and SOIC packages with RESET output: - MCP2022-330, LIN-compatible driver, 14-pin, 3.3V regulator - MCP2022-500, LIN-compatible driver, 14-pin, 5.0V regulator
Package Types
DFN-8, PDIP-8, SOIC-8 MCP2021
RXD CS/LWAKE VREG TXD 1 2 3 4 8 7 6 5 FAULT/TXE VBB LBUS VSS
PDIP-14, SOIC-14, TSSOP-14
RXD CS/LWAKE VREG TXD RESET NC NC 1 2 14 13 FAULT/TXE VBB LBUS VSS NC NC NC
MCP2022
3 4 5 6 7
12 11 10 9 8
(c) 2009 Microchip Technology Inc.
DS22018E-page 1
MCP2021/2
Block Diagram
Short Circuit Protection
Thermal Protection RESET Voltage Regulator VBB Ratiometric Reference Wake-Up Logic and Power Control
VREG
Internal Circuits
RXD ~30 k CS/LWAKE TXD FAULT/TXE Thermal Protection Short Circuit Protection OC LBUS VSS
DS22018E-page 2
(c) 2009 Microchip Technology Inc.
MCP2021/2
1.0 DEVICE OVERVIEW
1.2
1.2.1
Internal Protection
ESD PROTECTION
The MCP2021/2 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. The MCP2021/2 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN level logic, and vice versa. The LIN specification 2.0 requires that the transceiver of all nodes in the system be connected via the LIN pin, referenced to ground and with a maximum external termination resistance of 510 from LIN bus to battery supply. The 510 corresponds to 1 Master and 16 Slave nodes. The MCP2021-500 provides a +5V 50 mA regulated power output. The regulator uses a LDO design, is short-circuit-protected and will turn the regulator output off if it falls below 3.5V. The MCP2021/2 also includes thermal shutdown protection. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections, +43V load dump transients and double-battery jumps. The other members of the MCP2021-330 family output +3.3V at 50 mA with a turn-off voltage of 2.5V. (see Section 1.6 "Internal Voltage Regulator").
For component-level ESD ratings, please refer to the maximum operation specifications.
1.2.2
GROUND LOSS PROTECTION
The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a hi-impedance level.
1.2.3
THERMAL PROTECTION
The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. * Voltage regulator overload * LIN bus output overload * Increase in die temperature due to increase in environment temperature Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low).
1.1
1.1.1
Optional External Protection
REVERSE BATTERY PROTECTION
FIGURE 1-1:
An external reverse-battery-blocking diode should be used to provide polarity protection (see Example 1-1).
THERMAL SHUTDOWN STATE DIAGRAMS
Output Overload LIN bus shorted to VBB Operation Mode Transmitter Shutdown
1.1.2
TRANSIENT VOLTAGE PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode, between VBB and ground, with a 50 transient protection resistor (RTP) in series with the battery supply and the VBB pin serve to protect the device from power transients (see Example 1-1) and ESD events. While this protection is optional, it should be considered as good engineering practice.
Voltage Regulator Shutdown
Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP
EQUATION 1-1:
RTP <= (VBBmin - 5.5) / 250 mA. 5.5V = VUVLO + 1.0V, 250 mA is the peak current at power-on when VBB = 5.5V
(c) 2009 Microchip Technology Inc.
DS22018E-page 3
MCP2021/2
1.3 Modes of Operation
1.3.4 OPERATION MODE
For an overview of all operational modes, please refer to Table 1-1. In this mode, all internal modules are operational. The MCP2021/2 will go into the Power-down mode on the falling edge of CS/LWAKE.
1.3.1
POWER-ON-RESET MODE
Upon application of VBB, the device enters Power-OnReset mode (POR). During this mode, the part maintains the digital section in a reset mode and waits until the voltage on pin VBB rises above the "ON" threshold (Typ. 5.75V) to enter to the Ready mode. If during the operation, the voltage on pin VBB falls below the "OFF" threshold (Typ. 4.25V), the part comes back to the Power-On-Reset mode.
1.3.5
TRANSMITTER OFF MODE
Whenever the FAULT/TXE signal is low and the LBUS transmitter is off. The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, either by removing the internal fault condition or the CPU returning the FAULT/ TXE high. The transmitter will not be enabled if the FAULT/TXE pin is brought high when the internal fault is still present. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation.
1.3.2
POWER-DOWN MODE
In the Power-down mode, the transmitter and the voltage regulator are both off. Only the receiver section, and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest power mode. If any bus activity (e.g. a BREAK character) or CS/ LWAKE going to a high level should occur during Power-down mode, the device will immediately enter the Ready mode, enable the voltage regulator, and once the output has stabilized (approximately 0.3 ms to 1.2 ms), go to the Operation mode. Note: The above time interval < 1.2 ms assumes 12V VBB input and no thermal shutdown event.
1.3.5.1
Wake-up
The Wake-up sub module observes the LBUS in order to detect bus activity. Bus activity is detected when the voltage on the LBUS stays below a threshold of approximately 3V for at least a typical duration of 10 s. Such a condition causes the device to leave the Powerdown mode.
FIGURE 1-2:
CS/LWAKE = false
The part will also enter the Ready mode, followed by the Operation mode, if the CS/LWAKE pin should become active true (`1'). The part may only enter the Power-down mode after going through an Operation mode step.
OPERATIONAL MODES STATE DIAGRAMS
Power-down Mode Bus Activity OR CS/LWAKE = true
1.3.3
READY MODE
Upon entering the Ready mode, the voltage regulator and receiver threshold detect circuit are powered up. The transmitter remains in power down mode. The device is ready to receive data but not to transmit. If a microcontroller is being driven by the voltage regulator output, it will go through a Power-on Reset and initialization sequence. The LIN pin is in the recessive state. The device will stay in the Ready mode until the output of the voltage regulator has stabilized and CS/LWAKE pin is true (`1'). After VREG is OK and CS/LWAKE pin is true, the transmitter is enabled and the part enters the Operation mode. On Power-on of the VBB supply pin, the component will stay in the Ready mode if CS/LWAKE is low. If CS/ LWAKE is high, the device will immediately enter the Operation mode.
Transmitter Off Mode FAULT/TXE = false
CS/LWAKE = false Operation Mode Ready Mode VBBOK = true
FAULT/TXE = true
VREGOK = true AND CS/LWAKE = true Start
POR
Note:
While the MCP2021/2 is in shutdown, TXD should not be actively driven high or it may power internal logic through the ESD diodes and may damage the device.
DS22018E-page 4
(c) 2009 Microchip Technology Inc.
MCP2021/2
TABLE 1-1:
State POR READY OPERATION
OVERVIEW OF OPERATIONAL MODES
Transmitter OFF OFF ON Receiver OFF Activity Detect ON Voltage Regulator OFF ON ON Operation Read CS/LWAKE, if LOW, then READY, if HIGH, Operational mode If CS/LWAKE high level, then Operation mode Bus Off state Comments
If CS/LWAKE low level, then Power down Normal If FAULT/TXE low level, then Transmitter- Operation Off mode mode On LIN bus falling, go to READY mode. On CS/LWAKE high level, go to Operational mode If CS/LWAKE low level, then Power down If FAULT/TXE high, then Operation mode Low Power mode
POWER DOWN
OFF
Activity Detect ON
OFF
TRANSMITTEROFF
OFF
ON
1.4
Typical Applications
TYPICAL MCP2021 APPLICATION
+12 +12
EXAMPLE 1-1:
WAKE-UP 43V(5) 220 k VDD TXD RXD I/O I/O
(3)
RTP(5) CF Master Node Only +12
CG
VREG TXD
VBB 1 k
RXD CS/LWAKE FAULT/TXE VSS
LBUS 27V
(4)
LIN Bus
100nF
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation. . 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V..
(c) 2009 Microchip Technology Inc.
DS22018E-page 5
MCP2021/2
EXAMPLE 1-2: TYPICAL MCP2022 APPLICATION
+12 +12
WAKE-UP 43V(5) 220 k VDD TXD RXD I/O I/O INT 100 nF
(3)
RTP(5) CF Master Node Only +12
CG
VREG TXD
VBB 1 k
RXD CS/LWAKE FAULT/TXE RESET VSS
LBUS 27V
(4)
LIN Bus
VDD (6)
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V. 6: Required if CPU does not have internal pullup.
DS22018E-page 6
(c) 2009 Microchip Technology Inc.
MCP2021/2
EXAMPLE 1-3: TYPICAL MCP2022 APPLICATION
+12 +12
WAKE-UP 43V(5) 220 k VDD TXD RXD I/O I/O MCLR 100 nF 5V
(3)
RTP(5) CF Master Node Only +12
CG
VREG TXD
VBB 1 k
RXD CS/LWAKE 1 k FAULT/TXE RESET VSS
LBUS 27V
(4)
LIN Bus
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V.
FIGURE 1-3:
TYPICAL LIN NETWORK CONFIGURATION
40m + Return LIN bus
1 k VBB LIN bus MCP202X LIN bus MCP202X Slave 1 C Master C LIN bus MCP202X Slave 2 C LIN bus MCP202X Slave n <16 C
(c) 2009 Microchip Technology Inc.
DS22018E-page 7
MCP2021/2
1.5 Pin Descriptions
PINOUT DESCRIPTIONS
Devices Pin Name 8-Pin DFN, PDIP, SOIC 3 5 7 4 1 6 2 8 -- 14-Pin PDIP, SOIC, TSSOP 3 11 13 4 1 12 2 14 5 Pin Type Function
TABLE 1-1:
Normal Operation
VREG VSS VBB TXD RXD LBUS CS/LWAKE FAULT/TXE RESET
O P P I O I/O TTL OD OD
Power Output Ground Battery Supply Transmit Data Input (TTL) Receive Data Output (CMOS) LIN bus (bidirectional) Chip Select (TTL) Fault Detect Output, Transmitter Enable (OD) RESET signal Output (OD)
Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open-Drain output, P = Power, O = Output, I = Input
1.5.1 1.5.2 1.5.3
POWER OUTPUT (VREG) GROUND (VSS) BATTERY (VBB)
Positive Supply Voltage Regulator Output pin.
The internal LIN Receiver observes the activities on LIN bus, and generates the output signal RXD that follows the state of the LBUS. A 1st degree 1 MHz, lowpass input filter is placed to maintain EMI immunity.
Ground pin.
1.5.7
CS/LWAKE
Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator.
1.5.4
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up to VREG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. For extra bus security, TXD is internally forced to `1' when VREG is less than 1.8V (typ.). In case the thermal protection detects an over-temperature condition while the signal TXD is low, the transmitter is shutdown. The recovery from the thermal shutdown is equal to adequate cooling time.
Chip Select Input pin. A internal pull-down resistor will keep the CS/LWAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. The pin must see a high level to activate the transmitter. If CS/LWAKE= `0' when the VBB supply is turned on, the device stays in Ready mode (Low-power mode). In Ready mode, both the receiver and the voltage regulator are on and the LIN transmitter driver is off. If CS/LWAKE = `1' when the VBB supply is turned on, the device will proceed to the Operation mode as soon as the VREG output has stabilised. This pin may also be used as a local wake-up input (See Example 1-1). In this implementation, the microcontroller will set the I/O pin that controls the CS/ LWAKE as an high-impedance input. The internal pulldown resistor will keep the input low. An external switch, or other source, can then wake-up both the transceiver and the microcontroller. Note: CS/LWAKE should not be tied directly to VREG as this could force the MCP202x into Operation Mode before the microcontroller is initialized.
1.5.5
RECEIVE DATA OUTPUT (RXD)
The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin.
1.5.6
LIN BUS
The bidirectional LIN bus Interface pin is the driver unit for the LIN pin and is controlled by the signal TXD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled. To further reduce radiated emissions, the LBUS pin has corner-rounding control for both falling and rising edges.
DS22018E-page 8
(c) 2009 Microchip Technology Inc.
MCP2021/2
1.5.8 FAULT/TXE
Fault Detect output and Transmitter Enable input bidirectional pin. This pin is an open-drain output. Its state is defined as shown in Table 1-2. The transmitter driver is disabled whenever this pin is low (`0'), either from an internal fault condition or by external drive. This allows the transmitter to be placed in an off state and still allow the voltage regulator to operate. Refer to Table 1-1. The FAULT/TXE also signals a mismatch between the TXD input and the LBUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. This pin has an internal approximately 750 k. pull-up resistor of
Note 1: The FAULT/TXE pin is true (0) whenever the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. 2: FAULT/TXE is true (0) when VREG not OK and has disabled the LBUS output driver. The FAULT/TXE pin sampled at a rate faster than every 10 s.
TABLE 1-2:
TXD In L H L H x x RXD Out H H L L x x
FAULT/TXE TRUTH TABLE
FAULT/TXE LINBUS I/O VBB VBB GND GND VBB VBB Thermal Override OFF OFF OFF OFF ON x External Input H H H H H L Driven Output L H H H L x
Definition
FAULT, TXD driven low, LINBUS shorted to VBB (Note 1) OK OK OK, data is being received from the LINBUS FAULT, Tranceiver in thermal shutdown NO FAULT, the CPU is commanding the tranceiver to turn off the transmitter driver
Legend: x = don't care Note 1: The FAULT/TXE is valid after approximately 25 s after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays.
1.5.9
RESET
RESET is an open-drain output pin. This pin tracks an internal signal that tracks the internal system voltage has reached a valid, stable level. As long as the internal voltage is valid, this pin will remain high (`1'). When the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the RESET output to (`0'). When connected to a micro-controller input, this can provide a warning that the voltage regulator is shutting down (see Example 12). Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Example 1-3). In addition to monitoring the internal voltage, RESET is asserted immediately upon entering the Powerdown mode.
(c) 2009 Microchip Technology Inc.
DS22018E-page 9
MCP2021/2
1.6
1.6.1
Internal Voltage Regulator
5.0V REGULATOR
The MCP2021 has a low-drop-out voltage, positive regulator capable of supplying 5.00 VDC 3% at up to 50 mA of load current over the entire operating temperature range of -40C to +125C. With a load current of 50 mA, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 A with a full 50 mA load current when the input to output voltage differential is greater than +3.00V. The regulator requires an external output bypass capacitor for stability. See Figure 2-3 for correct capacity and ESR for stable operation. Designed for automotive applications, the regulator will protect itself from double-battery jumps and up to +43V load dump transients. The voltage regulator has both short-circuit and thermal shutdown protection built-in. Regarding the correlation between VBB, VREG and IDD, please refer to Figure 1-5 through 1-7. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the output Vreg will track the input down to approximately 3.5V, at which point the regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the Power-on Reset trip point. The MCP2021 will then monitor VBB and turn on the regulator when Vbb is 6.0V.
When the input voltage (VBB) drops below the differential needed to provide stable regulation, the output VREG) will track the input down to approximately +4.25V. The regulator will turn off the output at this point. This will allow PIC(R) microcontrollers, with internal POR circuits, to generate a clean arming of the Power-on Reset trip point. The regulator output will stay off until VBB is above +5.75 VDC. In the start phase, the device must see at least 6.0V to initiate operation during power up. In the Power-down mode, the VBB monitor will be turned off. Note: The regulator has an overload current limiting of approximately 100 mA. During a short circuit, the VREG is monitored. If VREG is lower than 3.5V, the VREG will turn off. After a recovery time of about three milliseconds, the VREG will be checked again. If there is no short circuit, (VREG > 3.5V) then the VREG will be switched back on.
The regulator has a thermal shutdown. If the thermal protection circuit detects an over temperature condition, and the signals TXD and RXD are LOW, or TXD is HIGH, the regulator will shut down. The recovery from the thermal shutdown is equal to adequate cooling time.
FIGURE 1-4:
VOLTAGE REGULATOR BLOCK DIAGRAM
VREG Sampling Network
Pass Element Fast Transient Loop Buffer VREF
VBB
VSS
DS22018E-page 10
(c) 2009 Microchip Technology Inc.
MCP2021/2
1.6.2 3.3V REGULATOR
A metal option provides for a alternate 3.30 VDC 3% at up to 50 mA of load current over the entire operating temperature range of -40C to +125C. All specifications given above for the 5.0V operation apply except for any difference noted here. The same input tracking of 4.25V applies the 3.3V regulator. Note: The regulator has an overload current limiting of approximately 100 mA. If VREG is lower than 2.5V, the VREG will turn off.
FIGURE 1-5:
VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
VBB V 8 6 4 2 0 VREG V 5.0 3.5 3 t
0 (1) Note 1: 2: 3: 4: (2) (3)
t
Start-up, VBB < 5.75V, regulator off. VBB > 5.75V, regulator on. VBB 5.5V, regulator tracks VBB VBB < 4.25V, regulator will turn off
(c) 2009 Microchip Technology Inc.
DS22018E-page 11
MCP2021/2
FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON POWER DIP
VBB V 12 8 6 4 3.5 2 0 VREG V 5 4 3.5 3 t
0 (1) Note 1: 2: 3: 4: (2) (3) (4)
t
Voltage regulator on. VBB 5.5V, regulator tracks VBB until VBB < 4.25V. VREG < 3.5V, regulator is off. VBB > 5.75V, regulator on.
DS22018E-page 12
(c) 2009 Microchip Technology Inc.
MCP2021/2
FIGURE 1-7: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION
IREG mA
50
0 VREG V
t
6 5.0 3.5 3
0 (1) Note 1: 2: (2)
t
IREG less than 50 mA, regulator on. After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached.
1.7
ICSPTM Considerations
The following should be considered when the MCP2021/2 is connected to pins supporting in-circuit programming: * Power used for programming the microcontroller can be supplied from the programmer, or from the MCP2021/2. * The voltage on VREG should not exceed the maximum output voltage of VREG.
(c) 2009 Microchip Technology Inc.
DS22018E-page 13
MCP2021/2
NOTES:
DS22018E-page 14
(c) 2009 Microchip Technology Inc.
MCP2021/2
2.0
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
VIN DC Voltage on RXD and TXD ........................................................................................................ -0.3 to VREG+0.3V VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VBB Battery Voltage, continuous ....................................................................................................................-0.3 to +30V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3) .............................................. minimum 9 kV ESD protection on LIN, VBB (Charge Device Model) (Note 2).............................................................................. 1500V ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4) ....................................................... 8 kV ESD protection on LIN, VBB (Machine Model) (Note 2) ..........................................................................................800V ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................ > 4 kV Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature .................................................................................................................................. -55 to +150C Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2009 Microchip Technology Inc.
DS22018E-page 15
MCP2021/2
2.2 DC Specifications
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C CLOADREG = 10 F Sym IBBQ -- VBB Transmitter-off Current IBBTO -- Min. Typ. 115 120 90 Max. 210 215 190 Units A A A Conditions IOUT = 0 mA, LBUS recessive VOUT = 3.3V With VREG on, transmitter off, receiver on, FAULT/ TXE = VIL, CS = VIH VOUT = 3.3V With VREG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) VBB = 12V, GND to VBB, VLIN = 0-18V
DC Specifications
Parameter Power VBB Quiescent Operating Current
-- VBB Power-down Current IBBPD --
95 16
210 26
A A
VBB Current with VSS Floating Microcontroller Interface High Level Input Voltage (TXD, FAULT/TXE) Low Level Input Voltage (TXD, FAULT/TXE) High Level Input Current (TXD, FAULT/TXE) Low Level Input Current (TXD, FAULT/TXE) Pull-up Current on Input (TXD) High Level Input Voltage (CS/LWAKE) Low Level Input Voltage (CS/LWAKE) High Level Input Current (CS/LWAKE) Low Level Input Current (CS/LWAKE) Pull-down Current on Input (CS/LWAKE) Note 1: 2: 3:
IBBNOGND
-1
--
1
mA
VIH
2.0 or (0.25VREG +0.8) -0.3 -2.5 -10 -3.0 0.7VREG -0.3
-- -- --
--
VREG +0.3 0.15 VREG
-- -- --
V
VIL IIH IIL IPUTXD VIH VIL IIH IIL IPDCS
-- -- -- -- -- -- -- -- --
V A A A V V A A A Input voltage = 0.8*VREG Input voltage = 0.2*VREG ~1.3M internal pull-down to VSS @ VIH = 3.5V Input voltage = 0.8*VREG Input voltage = 0.2*VREG ~800 k internal pull-up to VREG @ VIH = 0.7*VREG Through a current-limiting resistor
VBB 0.3VREG 7.0 3.0 6.0
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). For design guidance only, not tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition.
DS22018E-page 16
(c) 2009 Microchip Technology Inc.
MCP2021/2
2.2 DC Specifications (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C CLOADREG = 10 F Sym VIH(LBUS) VIL(LBUS) VHYS IOL(LBUS) IPU(LBUS) ISC VOH(LBUS) VOLLO (LBUS) IBUS_PAS_DOM Min. 0.6 VBB -8
--
DC Specifications
Parameter Bus Interface High Level Input Voltage Low Level Input Voltage Input Hysteresis Low Level Output Current Pull-up Current on Input Short Circuit Current Limit High Level Output Voltage Low Level Output Voltage Input Leakage Current (at the receiver during dominant bus level) Leakage Current (disconnected from ground) Leakage Current (disconnected from VBAT)
Typ.
-- -- -- -- -- -- -- -- --
Max. 18 0.4 VBB 0.175 VBB 200 180 200 VBB 0.2 VBB --
Units V V V mA A mA V V mA
Conditions Recessive state Dominant state VIH(LBUS) - VIL(LBUS) Output voltage = 0.1 VBB, VBB = 12V ~30 k internal pull-up @ VIH (LBUS) = 0.7 VBB (Note 1) VOH(LBUS) must be at least 0.8 VBB
40 5 50 0.8 VBB
--
-1
Driver off, VBUS = 0V, VBAT = 12V GNDDEVICE = VBAT, 0V < VBUS < 18V, VBAT = 12V VBAT = GND, 0 < VBUS < 18V, TA = -40C to +85C (Note 3) TA = +85C to +125C VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2
IBUS_NO_GND
-1
--
+1
mA
IBUS
--
--
10
A
50 Receiver Center Voltage Slave Termination Note 1: 2: 3: VBUS_CNT Rslave 0.475 VBB 20 0.5 VBB
30
A V k
0.525 VBB 47
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). For design guidance only, not tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition.
(c) 2009 Microchip Technology Inc.
DS22018E-page 17
MCP2021/2
2.2 DC Specification (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C CLOADREG = 10 F Sym VOUT VOUT2 Min. 4.85 -- Typ. 5.00 10 Max. 5.15 50 Units V mV Conditions 0 mA < IOUT < 50 mA, 5 mA < IOUT < 50 mA refer to Section 1.6 "Internal Voltage Regulator" IOUT = 0 mA, (Note 2) 1 VPP @10-20 kHz CLOAD = 10 f, ILOAD = 50 mA
DC Specifications
Parameter Voltage Regulator - 5.0V Output Voltage Load Regulation
Quiescent Current Power Supply Ripple Reject Output Noise Voltage
IVRQ PSRR
-- --
-- --
25 50
A dB
eN
--
--
100
VRMS 10 Hz - 40 MHz CFILTER = 10 f, CBP = 0.1 f, CLOAD 10 f, ILOAD = 50 mA V V V V See Figure 1-5
Shutdown Voltage Input Voltage to Maintain Regulation Input Voltage to Turn Off Output Input Voltage to Turn On Output Note 1: 2: 3:
VSD VBB VOFF VON
3.5 6.0 4.0 5.5
-- -- -- --
4.0 18.0 4.5 6.0
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). For design guidance only, not tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition.
FIGURE 2-1:
MCP2021-500 SAFE OPERATING RANGE
60
12V DFN
Voltage Regulator Load (mA)
50
12V SOIC
18V DFN
40
18V SOIC
30 20 10 0 -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 Temperature (C)
DS22018E-page 18
(c) 2009 Microchip Technology Inc.
MCP2021/2
2.2 DC Specification (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C CLOADREG = 10 F Sym VOUT VOUT1 VOUT2 Min. 3.20 -- -- Typ. 3.30 10 10 Max. 3.40 50 50 Units V mV mV Conditions 0 mA < IOUT < 50 mA IOUT = 1 mA, 6.0V < VBB < 18V 5 mA < IOUT < 50 mA Refer to Section 1.6 "Internal Voltage Regulator" IOUT = 0 mA, (Note 2) 1 VPP @10-20 kHz CLOAD = 10 f, ILOAD = 50 mA
DC Specifications
Parameter Voltage Regulator - 3.3V Output Voltage Line Regulation Load Regulation
Quiescent Current Power Supply Ripple Reject Output Noise Voltage
IVRQ PSRR
-- --
-- --
25 50
A dB
eN
--
--
100
VRMS 10 Hz - 40 MHz /Hz CFILTER = 10 f, CBP = 0.1 f CLOAD = 10 f, ILOAD = 50 mA V V V V See Figure 1-5
Shutdown Voltage Input Voltage to Maintain Regulation Input Voltage to Turn Off Output Input Voltage to Turn On Output Note 1: 2: 3:
VSD VBB VOFF VON
2.5 6.0 4.0 5.5
-- -- -- --
2.7 18.0 4.5 6.0
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). For design guidance only, not tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition.
FIGURE 2-2:
MCP2021-330 SAFE OPERATING RANGE
60 Voltage Regulator Load (mA)
12V DFN
50
12V SOIC 18V DFN
40 30 20 10 0 -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 Temperature (C)
18V SOIC
(c) 2009 Microchip Technology Inc.
DS22018E-page 19
MCP2021/2
FIGURE 2-3: ESR CURVES FOR LOAD CAPACITOR SELECTION
ESR Curves 10 Instable 1 ESR [ohm] Stable only
with Tantalum or Electrolytic cap.
Stable with 0.1 Instable
Tantalum, Electrolytic and Ceramic cap.
0.01 Instable 0.001 0.1 1 10 Load Capacitor [uF] 100 1000
DS22018E-page 20
(c) 2009 Microchip Technology Inc.
MCP2021/2
2.3 AC Specification
VBB = 6.0V to 18.0V; TA = -40C to +125C Sym tSLOPE tTRANSPD tRECPD tRECSYM Min. 3.5 -- -- -2.0 Typ. -- -- -- -- Max. 22.5 4.0 6.0 2.0 Units s s s s Test Conditions 7.3V <= VBB <= 18V tTRANSPD = max (tTRANSPDR or tTRANSPDF) tRECPD = max (tRECPDR or tRECPDF) tRECSYM = max (tRECPDF tRECPDR) tTRANSSYM = max (tTRANSPDF tTRANSPDR) tFAULT = max (tTRANSPD + tSLOPE + tRECPD) CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50 s. D1 = tBUS_REC(MIN) / 2 x tBIT) CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50 s. D2 = tBUS_REC(MAX) / 2 x tBIT) CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96 s. D3 = tBUS_REC(MIN) / 2 x tBIT) CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96 s. D4 = tBUS_REC(MAX) / 2 x tBIT) Parameter Slope rising and falling edges Propagation Delay of Transmitter Propagation Delay of Receiver Symmetry of Propagation Delay of Receiver rising edge w.r.t. falling edge Symmetry of Propagation Delay of Transmitter rising edge w.r.t. falling edge Time to sample of FAULT/ TXE for bus conflict reporting Duty Cycle 1 @20.0 kbit/sec AC CHARACTERISTICS
Bus Interface - Constant Slope Time Parameters
tTRANSSYM
-2.0
--
2.0
s
tFAULT
-- 39.6
-- --
32.5 --
s %tBIT
Duty Cycle 2 @20.0 kbit/sec
--
--
58.1
%tBIT
Duty Cycle 3 @10.4 kbit/sec
41.7
--
--
%tBIT
Duty Cycle 4 @10.4 kbit/sec
--
--
59.0
%tBIT
(c) 2009 Microchip Technology Inc.
DS22018E-page 21
MCP2021/2
2.3 AC Specification (Continued)
VBB = 6.0V to 18.0V; TA = -40C to +125C Sym tBDB tBACTVE tVEVR tCSOR tCSPD tSHUTDOWN tRPU tRPD Min. 5 100 -- -- -- 20 -- -- Typ. 10 250 -- -- -- -- -- -- Max. 20 500 1200 500 80 100 10.0 10.0 Units s s s s s s s s Test Conditions Bus debounce time After Bus debounce time (Note 1) (Note 1) Parameter Voltage Regulator Bus Activity Debounce time Bus Activity to Voltage Regulator Enabled Voltage Regulator Enabled to Ready Chip Select to Operation Ready Chip Select to Power-down Short circuit to shut-down RESET Timing VREG OK detect to RESET inactive VREG OK detect to RESET active Note 1: AC CHARACTERISTICS
Time depends on external capacitance and load.
2.4
Thermal Specifications
Parameter Symbol RECOVERY SHUTDOWN tTHERM JA JA JA JA JA JA Typ +140 +150 1.5 35.7 89.3 149.5 70 95.3 100 Max
-- --
THERMAL CHARACTERISTICS Units C C ms C/W C/W C/W C/W C/W C/W Test Conditions
Recovery Temperature Shutdown Temperature Short Circuit Recovery Time Thermal Package Resistances Thermal Resistance, 8L-DFN Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1:
5.0
-- -- -- -- -- --
The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2021 will go into thermal shutdown.
DS22018E-page 22
(c) 2009 Microchip Technology Inc.
MCP2021/2
2.5 Timing Diagrams and Specifications
BUS TIMING DIAGRAM
TXD 50% 50%
FIGURE 2-4:
LBUS .95VLBUS .50VBB .0++++++++++++++++++++++++---5V 0.0V TTRANSPDR
TTRANSPDF
TRECPDF RXD 50%
TRECPDR 50%
Internal TXD/RXD Compare FAULT Sampling
Match
Match
Match
Match
Match
TFAULT FAULT/TXE Output Stable Hold Value Stable Hold Value
TFAULT Stable
FIGURE 2-5:
REGULATOR CS/LWAKE TIMING DIAGRAM
CS/LWAKE TCSOR VREG VOUT
TCSPD
(c) 2009 Microchip Technology Inc.
DS22018E-page 23
MCP2021/2
FIGURE 2-6: REGULATOR BUS WAKE TIMING DIAGRAM
TVEVR LBUS
.4VBB
TBDB + TBACTVE VREG VOUT
FIGURE 2-7:
RESET TIMING DIAGRAM
VBB
6.0V 5.0V
5.0V 4.0V 3.5V VREG
TRPD RESET TRPU TRPU
TRPD
DS22018E-page 24
(c) 2009 Microchip Technology Inc.
MCP2021/2
FIGURE 2-8: CS/LWAKE TO RESET TIMING DIAGRAM
CS/LWAKE TCSOR VREG VOUT
TRPU RESET
TCSPD
FIGURE 2-9:
TYPICAL IBBQ VS. TEMPERATURE
0.2 0.15 Ibbq mA 0.1
Vbb = 6V Vbb = 7.3V
0.05 0 -40C
Vbb = 12V Vbb = 14.4V Vbb = 18V
25C
85C
125C
Temperature (C)
(c) 2009 Microchip Technology Inc.
DS22018E-page 25
MCP2021/2
FIGURE 2-10: TYPICAL IBBTO VS TEMPERATURE
0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 -40C
mA
Vbb = 6V Vbb = 7.3V Vbb = 12V Vbb = 14.4V Vbb = 18V
25C
85C
125C
Temperature (C)
FIGURE 2-11: TYPICAL IPD VS. TEMPERATURE
0.025 0.02 Ipd (mA) 0.015 0.01 0.005 0 -40C
Vbb = 6V Vbb = 7.3V Vbb = 12V Vbb = 14.4V Vbb = 18V
25C
85C
125C
Temperature (C)
DS22018E-page 26
(c) 2009 Microchip Technology Inc.
MCP2021/2
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (4x4) XXXXXXX XXXXXXX XXYYWW NNN Example: 202150 e3 E/MD^^ 0733 256
8-Lead DFN-S (6x5) XXXXXXX XXXXXXX XXYYWW NNN
Example: 2021500 e3 E/MF^^ 0733 256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: 2021500 e3 E/P^^256 0729
8-Lead SOIC (150 mil)
Example:
XXXXXXXX XXXXYYWW NNN
2021500E e3 SN^^0729 256
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
DS22018E-page 27
MCP2021/2
3.1 Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP2022) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example:
MCP2022-500 e3 E/P^^ 0729256
14-Lead SOIC (150 mil) (MCP2022)
Example:
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP2022-500 E/SL^^ e3 0729256
14-Lead TSSOP (MCP2022)
Example
XXXXXXXX YYWW NNN
2022500E 0729 256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22018E-page 28
(c) 2009 Microchip Technology Inc.
MCP2021/2
8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N e N L
b
E
K EXPOSED PAD
E2
1 NOTE 1
2 TOP VIEW D2
2
1
NOTE 1
BOTTOM VIEW
A3 A
A1 NOTE 2
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Exposed Pad Width Overall Width Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 D E2 E D2 b L K 0.00 0.25 0.30 0.20 0.00 0.80 0.00 MIN MILLIMETERS NOM 8 0.80 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.20 4.00 BSC 3.00 0.30 0.55 - 3.60 0.35 0.65 - 2.80 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-131C
(c) 2009 Microchip Technology Inc.
DS22018E-page 29
MCP2021/2
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DS22018E-page 30
(c) 2009 Microchip Technology Inc.
MCP2021/2
8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D b N K E EXPOSED PAD NOTE 1 1 2
e L N
E2
2 D2
1
NOTE 1
TOP VIEW
BOTTOM VIEW
A
A3
A1
NOTE 2
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Overall Width Exposed Pad Length Exposed Pad Width Contact Width Contact Length N e A A1 A3 D E D2 E2 b L 3.90 2.20 0.35 0.50 0.80 0.00 MIN MILLIMETERS NOM 8 1.27 BSC 0.85 0.01 0.20 REF 5.00 BSC 6.00 BSC 4.00 2.30 0.40 0.60 4.10 2.40 0.48 0.75 - 1.00 0.05 MAX
Contact-to-Exposed Pad K 0.20 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-122B
(c) 2009 Microchip Technology Inc.
DS22018E-page 31
MCP2021/2
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DS22018E-page 32
(c) 2009 Microchip Technology Inc.
MCP2021/2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N
NOTE 1 E1
1
2 D
3 E
A
A2
A1
L
c
e b1 b
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .348 .115 .008 .040 .014 - MIN
eB
INCHES NOM 8 .100 BSC - .130 - .310 .250 .365 .130 .010 .060 .018 - .210 .195 - .325 .280 .400 .150 .015 .070 .022 MAX
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B
(c) 2009 Microchip Technology Inc.
DS22018E-page 33
MCP2021/2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D e N
E E1
NOTE 1 1 2 3 b h c h
A
A2
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN
MILLIMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B
DS22018E-page 34
(c) 2009 Microchip Technology Inc.
MCP2021/2
/HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ
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(c) 2009 Microchip Technology Inc.
DS22018E-page 35
MCP2021/2
14-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N
NOTE 1
E1
1
2
3 D E
A
A2
L A1 b b1 e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .735 .115 .008 .045 .014 - MIN INCHES NOM 14 .100 BSC - .130 - .310 .250 .750 .130 .010 .060 .018 - .210 .195 - .325 .280 .775 .150 .015 .070 .022 MAX
c
eB
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-005B
DS22018E-page 36
(c) 2009 Microchip Technology Inc.
MCP2021/2
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 2 b h 3
e h c
A
A2
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN
MILLIMETERS NOM 14 1.27 BSC - - - 6.00 BSC 3.90 BSC 8.65 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-065B
(c) 2009 Microchip Technology Inc.
DS22018E-page 37
MCP2021/2
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DS22018E-page 38
(c) 2009 Microchip Technology Inc.
MCP2021/2
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 e b c A A2
A1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c
L1
MILLIMETERS MIN NOM 14 0.65 BSC - 0.80 0.05 4.30 4.90 0.45 0 0.09 - 1.00 - 6.40 BSC 4.40 5.00 0.60 1.00 REF - - 8 0.20 4.50 5.10 0.75 1.20 1.05 0.15 MAX
L
Lead Width b 0.19 - 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-087B
(c) 2009 Microchip Technology Inc.
DS22018E-page 39
MCP2021/2
NOTES:
DS22018E-page 40
(c) 2009 Microchip Technology Inc.
MCP2021/2
APPENDIX A: REVISION HISTORY
Revision B (August 2007)
The following is the list of modifications: 1. 2. 3. 4. 5. 6. Modified Block Diagram on page 2. Section 1.3.5 "Transmitter OFF Mode": Deleted text in 1st paragraph. Example 1-1: Removed +5V notation. Section 1.5 "Pin Descriptions": Removed 10pin DFN, MSOP column from table. Section 1.5.8 "Fault/TXE": Deleted text from 2nd paragraph. Section 3.0 "Packaging Information": Added 8-lead 4x4 and 6x5 DFN and 14-lead TSSOP packages. Updated package outline drawings and added drawings for 8-lead DFN and 14-lead TSSOP drawings.
Revision E (February 2009)
The following is the list of modifications. 1. 2. 3. 4. 5. 6. 7. Added Example 1-2 and Example 1-3. Updated Section 1.5.9 "RESET". Updated Section 1.7 "ICSPTM Considerations". Updated Section 2.1 "Absolute Maximum Ratings". Updated Section 2.2 "DC Specifications" and Section 2.3 "AC Specification". Added FIGURE 2-3: "ESR Curves For Load Capacitor Selection". Updated the Product Identification System section.
Revision A (November 2005)
* Original Release of this Document.
Revision D (July 2008)
The following is the list of modifications. 1. 2. 3. Updated ESD specs under `Absolute DC'. Updated notes in Example 1-1. Updated Package Outline Drawings.
Revision C (April 2008)
The following is the list of modifications. 1. 2. 3. 4. Added LIN2.1 and J2602 compliance statement to Features section. Added recommended RC network for CS/ LWAKE in Example 1-1. Updated 2.1 Absolute Maximum Ratings to reflect current test results. Updated 2.2 DC Specifications and 2.3 AC Specifications to reflect current production device. Added 8-Lead SOIC Landing Pattern Outline drawing.
5.
(c) 2009 Microchip Technology Inc.
DS22018E-page 41
MCP2021/2
NOTES:
DS22018E-page 42
(c) 2009 Microchip Technology Inc.
MCP2021/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples:
a) b) c) d) e) f) g) h) i) 3.3V, 8L-SOIC pkg. 3.3V, 8L-PDIP pkg. 5.0V, 8L-DFN-S pkg. 5.0V, 8L-SOIC pkg. 5.0V, 8L-DFN pkg. 5.0V, 8L-PDIP pkg. Tape and Reel, 3.3V, 8L-SOIC pkg. MCP2021T-500E/MD: Tape and Reel, 5.0V, 8L-DFN pkg. MCP2021T-500E/SN: Tape and Reel, 5.0V, 8L-SOIC pkg. 3.3V, 14L-SOIC pkg. 3.3V, 14L-PDIP pkg. 5.0V, 14L-SOIC pkg. 5.0V, 14L-PDIP pkg. Tape and Reel, 3.3V, 14L-SOIC pkg. MCP2022T-500E/SL: Tape and Reel, 5.0V, 14L-SOIC pkg. MCP2022T-500E/ST: Tape and Reel, 5.0V, 14L-TSSOP pkg. MCP2022-330E/SL: MCP2022-330E/P: MCP2022-500E/SL: MCP2022-500E/P: MCP2022T-330E/SL: MCP2021-330E/SN: MCP2021-330E/P: MCP2021-500E/MF: MCP2021-500E/SN: MCP2021-500E/MD: MCP2021-330E/P: MCP2021T-330E/SN:
Device:
MCP2021: LIN Transceiver with Voltage Regulator MCP2021T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only) MCP2022: LIN Transceiver with Voltage Regulator MCP2022T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only)
Temperature Range:
E
= -40C to +125C
Package:
MD MF P SN SL ST
= = = = = =
Plastic Micro Small Outline (4x4), 8-lead Plastic Micro Small Outline (6x5), 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC, (150 mil Body), 14-lead Plastic Thin Shrink Small Outline, 14-lead
a) b) c) d) e) f) g)
(c) 2009 Microchip Technology Inc.
DS22018E-page 43
MCP2021/2
NOTES:
DS22018E-page 44
(c) 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2009 Microchip Technology Inc.
DS22018E-page 45
Worldwide Sales and Service
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
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EUROPE
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02/04/09
DS22018E-page 46
(c) 2009 Microchip Technology Inc.

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